| Term | Definition |
|---|---|
| Computer architecture | Also known as the Instruction Set Architecture (ISA). The set of rules, methods and procedures that define the functionality, organization and implementation of a computer system as seen by the machine-language programmer or compiler writer. It is the contract between software and hardware · a specification that remains constant across implementations. |
| Computer organization | The actual implementation of a computer architecture: how the functional units are constructed, interconnected and controlled to realize the specified architecture, and the engineering decisions affecting cost/performance, power consumption and physical size. |
| Logic gate | The fundamental building block of digital circuits · a device that performs a boolean function, a logical operation on one or more binary inputs producing a single binary output. |
| Logic expression minimization | Simplifying boolean equations to reduce the hardware required for a digital circuit; it cuts production cost, minimizes heat generation and improves speed. |
| Karnaugh map | A visual, graphical matrix method used to simplify boolean expressions of up to 4–6 variables, in which groupings are made in powers of 2ⁿ to find the minimal sum of products. |
| Majority vote circuit | A digital circuit in which the majority of the inputs determines the output. |
| RTL | Register Transfer Language · a symbolic notation used to describe the internal organization, data flow and execution of micro-operations between hardware registers. It bridges high-level architectural design and concrete logic-gate implementation. |
| Micro-operation | An elementary operation performed on data in CPU registers during a clock pulse · arithmetic, logic or shift. |
| Control function | A boolean condition that dictates when a transfer occurs; written before a colon, e.g. P: R2 ← R1. |
| Memory hierarchy | An organizational pyramid that categorizes data storage by speed, cost and capacity, so the processor can access frequently used data at very high speed without sacrificing the massive capacity needed for a user's whole library of files. |
| Cache memory | A high-speed, volatile hardware component situated between the CPU and main memory (RAM), storing temporary copies of frequently accessed data and instructions so the processor retrieves them instantly, reducing latency and improving performance. |
| Cache hit / miss | Hit · the CPU checks the cache first and the data is found, so it is retrieved almost instantly (nanoseconds). Miss · the data is not in the cache, so the CPU must fetch it from the slower RAM, and it is then copied into the cache for future use. |
| Locality of reference | A program's tendency to repeatedly access the same memory locations, or nearby ones, over a short period. It is the foundation of cache memory design. |
| Performance | A measure of how quickly and efficiently a computer system executes a given workload, defined by speed (how fast a task completes) and throughput (how much work is done in a given time). Mathematically the reciprocal of execution time. |
| Sign bit | The bit used to represent whether a number is positive or negative, since a digital circuit has only 0s and 1s and no "−" symbol. It is the MSB: 1 = negative, 0 = positive. |
| Unsigned number | A binary number that does not allow negative values; an n-bit unsigned number has 2ⁿ unique codes and a range of 0 to 2ⁿ − 1. |
Both lists were dictated in full. A question asking you to differentiate architecture from organization is answered by defining both, giving the table, then quoting a few items from each list.
| Basis | Computer architecture (ISA) | Computer organization |
|---|---|---|
| What it answers | What the machine does · its behaviour as seen by a program | How the machine does it · how the units are built and wired |
| Level | Abstract specification / interface | Concrete implementation |
| Visible to | The machine-language programmer and the compiler writer | The hardware designer / engineer |
| Stability | Constant across different implementations of the same architecture | Varies between models that share one architecture |
| Driven by | Functional requirements · the software contract | Engineering trade-offs: cost/performance, power, physical size |
| Example | x86-64 · software compiled for it runs on any processor implementing it | Two x86-64 chips with different cache sizes, pipeline depths and clock speeds |
| A | B | A·B AND | A+B OR | (A·B)' NAND | (A+B)' NOR | A⊕B XOR | (A⊕B)' XNOR |
|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 |
| 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 |
| 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 |
| 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |
The NOT gate has its own two-row table: 0 → 1, 1 → 0.
C = (A·B)'.C = (A+B)'.1 input → 2 rows · 2 inputs → 4 rows · 3 inputs → 8 rows. Fill the input columns by counting up in binary · 000, 001, 010, 011, 100, 101, 110, 111 · so no combination is missed.
The exclusive-OR is not primitive · it is assembled from two NOTs, two ANDs and one OR, which is exactly what its sum-of-products expression says:
Read the expression straight off the truth table: take every row where the output is 1, write the product of the inputs (complemented where the input is 0), and OR those products together. That procedure is the sum of products (SOP), and it works for any truth table.
┌─────┐
A ─┬──────►│ AND ├──┐ (A·B')
│ ┌───►│ │ │
│ │ └─────┘ │ ┌────┐
│ │ ┌──o B' ├─►│ OR ├──► Y
│ └──┤ └────┘
B ─┴─────┼──o A' │
┌─────┐ │
│ AND ├───────┘ (A'·B)
└─────┘
| Law | AND form | OR form | What it does for you |
|---|---|---|---|
| Identity | A·1 = A | A+0 = A | Removes a redundant constant |
| Null | A·0 = 0 | A+1 = 1 | Collapses a whole term to a constant |
| Idempotent | A·A = A | A+A = A | Deletes a duplicated literal |
| Complement | A·A' = 0 | A+A' = 1 | The workhorse of minimization · this is what makes grouping work |
| Absorption | A·(A+B) = A | A + A·B = A | Swallows the longer term entirely |
| Distributive | A·(B+C) = A·B + A·C | A + B·C = (A+B)(A+C) | Factors a common variable out of two terms |
| De Morgan | (A·B)' = A' + B' | (A+B)' = A'·B' | Pushes a bar through a bracket · break the bar, change the sign |
A·1 = A, build the truth table. Anywhere a 1 appears as a column head it is 1 (true) all the way down that column, and a 0 is 0 (false) all the way down. Then compare the result column with the column for A: if they are identical, the identity holds.
A │ 1 │ A·1 │ 0 │ A+0 A·1 matches A ✓ ──┼───┼─────┼───┼───── A+0 matches A ✓ 0 │ 1 │ 0 │ 0 │ 0 1 │ 1 │ 1 │ 0 │ 1
Opening sentence: minimization simplifies boolean equations to reduce the hardware required for digital circuits; it cuts production cost, minimizes heat generation and improves speed.
A majority vote circuit outputs 1 when the majority of its inputs are 1. With three inputs, that means any two or more.
| # | A | B | C | F | Minterm |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | |
| 1 | 0 | 0 | 1 | 0 | |
| 2 | 0 | 1 | 0 | 0 | |
| 3 | 0 | 1 | 1 | 1 | A'BC ① |
| 4 | 1 | 0 | 0 | 0 | |
| 5 | 1 | 0 | 1 | 1 | AB'C ② |
| 6 | 1 | 1 | 0 | 1 | ABC' ③ |
| 7 | 1 | 1 | 1 | 1 | ABC ④ |
F = A'BC + AB'C + ABC' + ABC Groupings · pair terms differing in ONE variable: ① and ④ ⇒ A'BC + ABC ⇒ BC(A'+A) = BC ③ and ④ ⇒ ABC' + ABC ⇒ AB(C'+C) = AB ② and ④ ⇒ AB'C + ABC ⇒ AC(B'+B) = AC ∴ F = BC + AB + AC
X + X' = 1 together with the identity law Y·1 = Y. Note that minterm ④ is reused in all three groupings · a minterm may belong to more than one group, because X + X = X (idempotent). Four 3-input AND gates and one OR gate become three 2-input AND gates and one OR gate.
BC
A \ 00 01 11 10
───┼────┼────┼────┼────
0 │ 0 │ 1 │ 3 │ 2 │ ← decimal row numbers
───┼────┼────┼────┼────
1 │ 4 │ 5 │ 7 │ 6 │
───┴────┴────┴────┴────
Class result: F = AB' + BC'
| Group size | Variables cancelled | Term length (3-variable map) |
|---|---|---|
| 1 cell | 0 | 3 literals, e.g. A'BC |
| 2 cells | 1 | 2 literals, e.g. BC |
| 4 cells | 2 | 1 literal, e.g. A |
| 8 cells | 3 | The function is simply 1 |
Always make the groups as large as legally possible · a bigger group means a shorter term and fewer gates. Then check every 1 is covered by at least one group.
RTL is a symbolic notation used in computer architecture to describe the internal organization, data flow and execution of micro-operations between hardware registers. It bridges the gap between high-level architectural design and concrete logic-gate implementation, allowing engineers to concisely map out how data moves through a CPU during each clock cycle.
| Symbol | Meaning |
|---|---|
| Capital letters | Denote specific hardware registers · R1, R2, PC, MAR |
| Arrow ← | A unidirectional transfer from the source on the right to the destination on the left |
| Parenthesis ( ) | A distinct sub-part or individual bits of a register · R1(0-7) is the lower 8 bits |
| Colon : | Terminates a control function · the operation executes only if the preceding condition is true |
| Comma , | Separates micro-operations that execute simultaneously in a single clock cycle |
Bus ← R1 R1 drives the system bus R2 ← Bus R2 latches data from the bus
| Type | What it does | Example |
|---|---|---|
| Register transfer | Moves binary data from one processor register to another without modifying it | R2 ← R1 |
| Arithmetic | Numeric operations · addition, subtraction, increment · on data inside the registers | R3 ← R1 + R2 |
| Logic | Bitwise operations (AND, OR, XOR, NOT) manipulating bits independently within the register | R ← R1 ∧ R2 |
| Control function | Boolean conditions dictating when a transfer occurs | P: R2 ← R1 |
Micro-operations are elementary operations performed on data in CPU registers during a clock pulse · arithmetic, logic and shift.
| Statement | RTL |
|---|---|
If K = 1 then transfer R1 into R2 | K: R2 ← R1 |
If K = 1 then R2 ← R1, otherwise R2 ← R4 | K: R2 ← R1 · K': R2 ← R4 - the else branch uses the complement of the control signal |
If Z = 1 AND C = 0 then increment the program counter | Z·C': PC ← PC + 1 - AND of conditions is written as a product |
| Transfer R1 to R2 and R3 to R4 in the same clock cycle | R2 ← R1, R4 ← R3 - the comma means simultaneously |
| Load the lower 8 bits of R1 into R2 | R2 ← R1(0-7) |
The PC keeps track of the next instruction to be fetched by the CPU from memory. The fetch/execute cycle is: Fetch (PC supplies the address) → Decode (the control unit interprets the instruction) → Execute.
| Base | Name | Digits |
|---|---|---|
| 10 | Decimal / denary | 0 1 2 3 4 5 6 7 8 9 |
| 8 | Octal | 0 1 2 3 4 5 6 7 |
| 2 | Binary | 0 1 |
| 16 | Hexadecimal | 0–9 then A B C D E F (A = 10 … F = 15) |
4832₁₀ = 4×10³ + 8×10² + 3×10¹ + 2×10⁰ 21673₈ = 2×8⁴ + 1×8³ + 6×8² + 7×8¹ + 3×8⁰ 10111001₂= 1×2⁷ + 1×2⁵ + 1×2⁴ + 1×2³ + 1×2⁰
Every base works the same way: the digit is multiplied by the base raised to its position, counting from 0 at the right-hand end. Fractions continue with negative powers: 8⁻¹, 8⁻², 8⁻³ …
4832 to base 8 4832 to base 16
8│4832 16│4832
8│ 604 · 0 16│ 302 · 0
8│ 75 · 4 16│ 18 · 14 (E)
8│ 9 · 3 16│ 1 · 2
8│ 1 · 1 │ 0 · 1
│ 0 · 1
read UP: 12E0₁₆
read UP: 11340₈
Divide by the target base, write the remainder beside each line, stop at 0, then read the remainders upwards. For hexadecimal, convert remainders 10–15 into A–F before writing them down.
| Base | 4832 becomes | Check by expanding it back to base 10 |
|---|---|---|
| 2 | 1001011100000₂ | 2¹² + 2⁹ + 2⁷ + 2⁶ + 2⁵ = 4096 + 512 + 128 + 64 + 32 = 4832 ✓ |
| 8 | 11340₈ | 1×4096 + 1×512 + 3×64 + 4×8 + 0 = 4832 ✓ |
| 16 | 12E0₁₆ | 1×4096 + 2×256 + 14×16 + 0 = 4096 + 512 + 224 = 4832 ✓ |
| fraction | 11340.0012₈ | = 4832.00244140625₁₀ · see the fraction method below |
Convert 0.00244140625 to base 8 0.00244140625 × 8 = 0.01953125 → 0 0.01953125 × 8 = 0.15625 → 0 0.15625 × 8 = 1.25 → 1 0.25 × 8 = 2.0 → 2 stop ∴ 0.00244140625₁₀ = 0.0012₈
Multiply the fraction by the base, take the integer part as the next digit, carry the fractional remainder forward, and read the digits downwards · the opposite direction to the whole-number method.
Octal ↔ binary · group in THREES from the right
4362₈ = 100 011 110 010 = 100011110010₂
1001011100000₂ → 1 001 011 100 000 → 11340₈
Hex ↔ binary · group in FOURS from the right
1001011100000₂ → 0001 0010 1110 0000
1 2 E 0 → 12E0₁₆
Pad the leftmost group with leading zeros. Octal and hexadecimal exist precisely because they are compact shorthands for binary · this is why the conversion is pure grouping and needs no arithmetic.
0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 10 (0 carry 1)
1 + 1 + 1 = 11 (1 carry 1)
10111₂ (23)
+ 11101₂ (29)
────────
110100₂ (52) ✓
246₈ (166)
− 127₈ ( 87)
───────
117₈ ( 79) ✓
When you borrow in base 8 you borrow 8, not 10. Check the answer by converting all three numbers to decimal.
336₈ (222)
× 227₈ (151)
────────
3022 336₈ × 7₈
674 336₈ × 2₈ ←shift
+ 674 336₈ × 2₈ ←shift
────────
101362₈ (33522) ✓
In base 8, carry whenever a column reaches 8 · divide by 8, write the remainder, carry the quotient.
In a real digital circuit there is no "−" symbol · the hardware only has 0s and 1s. So one bit, the most significant bit (MSB), is used to carry the sign. A number that never goes negative is unsigned; one that may go negative is signed. The same bit pattern means different values under different schemes, so you must always state which scheme is in use.
| n | Unique codes | Range |
|---|---|---|
| 4 | 16 | 0 … 15 |
| 8 | 256 | 0 … 255 |
| 16 | 65 536 | 0 … 65 535 |
A 4-bit number has 16 codes but its largest value is 15 · because one code is spent on 0. That is exactly why the maximum is 2ⁿ − 1 and not 2ⁿ. It is the single most common slip on this topic.
| Value | Signed magnitude | One's complement | Two's complement |
|---|---|---|---|
| +3 | 0011 | 0011 | 0011 |
| −3 | 1011 | 1100 | 1101 |
| +7 | 0111 | 0111 | 0111 |
| −7 | 1111 | 1000 | 1001 |
| +0 | 0000 | 0000 | 0000 |
| −0 | 1000 | 1111 | 0000 |
Positive numbers are identical in all three schemes. Note the last row: signed magnitude and one's complement both have two representations of zero; two's complement has only one · which is the main reason real hardware uses it.
| Scheme | Rule for a negative number | Worked: −56 (56₁₀ = 0111000₂) |
|---|---|---|
| Signed magnitude | Write the magnitude in binary, then set the MSB to 1. The remaining n−1 bits are preserved and hold the magnitude. | 0111000 → change the first digit 0 to 1 → 1111000₂ |
| One's complement | The MSB represents the sign; invert every bit of the positive form (negative numbers only). | 0111000 → negate → 1000111₂ |
| Two's complement | Invert every bit, then add 1. The MSB is the sign bit. | 0111000 → 1000111 → +1 → 1001000₂ |
11111111₂ · One's complement: 10000000₂ · Two's complement: 10000001₂ (invert to 10000000, then add 1).
| Level | Speed | Capacity | Purpose |
|---|---|---|---|
| CPU registers | Extremely fast (sub-nanosecond) | Tiny (bytes; 16–64 bits) | Built inside the CPU core to hold the exact data being executed in the current cycle |
| Cache (L1/L2/L3) | Very fast (SRAM) | Small–moderate (KB–MB) | Buffer between registers and system RAM; uses locality to preload frequently and recently used data |
| Main memory (RAM) | Moderate | Moderate–large (16–64 GB) | Primary working memory for the OS and running applications |
| Secondary storage | Slow (milliseconds) | Massive (terabytes) | Non-volatile SSDs and HDDs; retains data when powered down; long-term repository |
| Tertiary storage | Very slow | Infinite (scalable) | Offline, archival and backup data · tape libraries, optical disks |
Cache memory is a high-speed, volatile hardware component situated between the CPU and main memory (RAM). It stores temporary copies of frequently accessed data and instructions so the processor can retrieve them instantly, significantly reducing processing latency and improving system performance. It works because of locality of reference.
| Level | Location | Size | Speed |
|---|---|---|---|
| L1 | Directly on the CPU core | 2 KB – 64 KB per core | Fastest, smallest |
| L2 | Inside or immediately outside the core | 256 KB – 512 KB | Bridge for the L1 cache |
| L3 | Shared among all cores | 1 MB – 8 MB or higher | Largest but slowest; feeds into L2 |
Cache hit · the CPU checks the cache first and finds the data, retrieving it in nanoseconds. Cache miss · the data is absent, so the CPU fetches from slower RAM and the block is then copied into the cache for future use.
Other caching: disk/file cache (the OS holds recently read files in RAM) and browser cache (images, scripts and page data kept in local storage).
| Mapping | How a memory block is placed |
|---|---|
| Direct mapped | Each block is mapped to exactly one cache location. |
| Fully associative | Similar in structure, but a memory block may be mapped to any cache location rather than a pre-specified one. |
| Set associative | A compromise between the two: each block maps to a subset of cache locations. Also called N-way set associative · a main-memory location may be cached to any of N locations in the L1 cache. |
| Policy | Mechanism | Consequence |
|---|---|---|
| Write-through | Data written to both the cache and main memory at the same time | More writing, so latency upfront, but memory stays consistent |
| Write-back | Data written to the cache only at first; it may reach main memory later, but need not, and this does not inhibit the interaction | More efficient, but data may be inconsistent between cache and main memory |
Locality of reference (the principle of locality) describes a program's tendency to repeatedly access the same memory locations, or nearby ones, over a short period. It is the foundation for cache memory design, allowing CPUs to fetch frequently used data ahead of time and dramatically increasing system speed.
Other forms of locality: sequential locality · branch locality.
In computer architecture, performance measures how quickly and efficiently a computer system executes a given workload or program. It is primarily defined by speed · how fast a task completes · and throughput · how much work is done in a given time.
| Factor | Definition | Determined by |
|---|---|---|
| Instruction Count (IC) | Total number of instructions executed in a program | The software compiler and the ISA |
| Cycles Per Instruction (CPI) | Average number of clock cycles to execute one instruction | Hardware design and pipeline efficiency |
| Clock Cycle Time | Duration of a single clock tick · the inverse of clock frequency (e.g. 3.0 GHz) | Semiconductor technology and hardware engineering |
The law is "iron" because all three factors multiply · improving one while worsening another may leave performance unchanged. A compiler that halves IC but doubles CPI wins nothing.
Clock cycle time = 1 / 3.0×10⁹ = 0.333 ns
CPU Time = 2×10⁹ × 1.5 × 0.333×10⁻⁹ s
= 1.0 second
Worked example 2 · relative performance. Machine A runs a program in 10 s, Machine B in 15 s.
Relative Performance = Exec B / Exec A
= 15 / 10 = 1.5
∴ Machine A is 1.5 times faster than Machine B
Worked example 3 · MIPS. Same program as example 1:
MIPS = IC / (Execution Time × 10⁶)
= 2×10⁹ / (1.0 × 10⁶)
= 2000 MIPS
Other performance indicators: MIPS · Million Instructions Per Second · FLOPS · Floating Point Operations Per Second.
R2 → R1 when you mean R2 ← R1. The arrow points to the destination.K': R2 ← R4, not K.